Ultra-low power FinFET based SRAM cell employing sharing current concept

Article history: Received 13 May 2013 Received in revised form 3 October 2015 Accepted 26 November 2015 Available online xxxx This paper proposes a new ultra-low leakage, single-ended FinFET-based SRAM cell to improve the stability and read ON/OFF current ratio. The design employs a power gate transistor that shares the read path and main body current to improve the cell stability (SNM) by reforming the butterfly curves. In addition adjusting the tail transistor strength reduces the hold power, suppresses the variability of the cell by acting as internal feedback and improves write ability in active mode by decreasing the voltage drop over the cell. The proposed architecture redesigns the read path circuit and leverages voltage boosting for biasing, effectively eliminating access transistor leakage in read, write and hold modes. With 20 nm FinFET technology, the results show that in above threshold (near threshold) region, the proposed structure has at least 2.2× (3.5×) lower static power, with 15% (16%) lower static power variation with respect to other state-of-the-art 10T cells. Additionally, our results show that the proposed cell improves the ON/OFF current ratio by at least 20× and 6.5× compared to prior designs in above threshold and near threshold regions respectively. © 2015 Published by Elsevier Ltd.